1. Field of the Invention
The present invention generally relates to the art of microelectronic integrated circuits, and more specifically to a method for erasing a flash Electrically Erasable Programmable Read-Only Memory (EEPROM).
2. Description of the Related Art
A microelectronic flash or block erase Electrically Erasable Programmable Read-Only Memory (Flash EEPROM) includes an array of cells which can be independently programmed and read. The size of each cell and thereby the memory are made small by omitting select transistors which would enable the cells to be erased independently. All of the cells are erased together as a block.
A memory of this type includes individual Metal-Oxide-Semiconductor (MOS) field effect transistor memory cells, each of which includes a source, drain, floating gate and control gate to which various voltages are applied to program the cell with a binary 1 or 0, or erase all of the cells as a block.
The cells are connected in a rectangular array of rows and columns, with the control gates of the cells in a row being connected to a respective wordline and the drains of the cells in a column being connected to a respective bitline. The sources of the cells are connected together. This arrangement is known as a NOR memory configuration.
A cell is programmed by applying, typically, 9 V to the control gate, 5 V to the drain and grounding the source, which causes hot electrons to be injected from the drain depletion region into the floating gate. Upon removal of the programming voltages, the injected electrons are trapped in the floating gate and create a negative charge therein which increases the threshold voltage of the cell to a value in excess of approximately 4 V.
The cell is read by applying typically 5 V to the control gate, 1 V to the bitline to which the drain is connected, grounding the source, and sensing the bitline current. If the cell is programmed and the threshold voltage is relatively high (4 V), the bitline current will be zero or at least relatively low. If the cell is not programmed or erased, the threshold voltage will be relatively low (2 V), the control gate voltage will enhance the channel, and the bitline current will be relatively high.
A cell can be erased in several ways. In one arrangement, a cell is erased by applying typically 12 V to the source, grounding the control gate and allowing the drain to float. This causes the electrons which were injected into the floating gate during programming to be removed by Fowler-Nordheim tunneling from the floating gate through the thin tunnel oxide layer to the source. Alternatively, a cell can be erased by applying a negative voltage on the order of -10 V to the control gate, applying 5 V to the source and allowing the drain to float.
A problem with the conventional flash EEPROM cell arrangement is that due to manufacturing tolerances, some cells become over-erased before other cells become erased sufficiently. The floating gates of the over-erased cells are depleted of electrons and become positively charged. This causes the overerased cells to function as depletion mode transistors which cannot be turned off by normal operating voltages applied to their control gates, and introduces leakage during subsequent program and read operations.
More specifically, during program and read operations only one wordline which is connected to the control gates of a row of cells is held high at a time, while the other wordlines are grounded. However, a positive voltage is applied to the drains of all of the cells. If the threshold voltage of an unselected cell is zero or negative, leakage current will flow through the source, channel and drain of the cell.
This undesirable effect is illustrated in FIG. 1. The drains of a column of floating gate cell transistors T.sub.0 to T.sub.m are connected to a bitline BL, which is itself connected to a bitline driver 1. The sources of the transistors T.sub.0 to T.sub.m are typically connected to ground. One of the transistors T.sub.0 to T.sub.m is selected for a program or read operation by applying a positive voltage, e.g. 5 V, to its control gate which turns on the transistor. The control gates of the unselected transistors are connected to ground.
As viewed in FIG. 1, 5 V is applied to the transistor T.sub.1 which turns it on. A current I.sub.1 flows through the transistor T.sub.1 from ground through its source, channel (not shown) and drain and through the bitline BL to the driver 1. Ideally, the bitline current I.sub.BL should be equal to I.sub.1.
However, if one or more of the unselected transistors, e.g. the transistor T.sub.2 as illustrated in FIG. 1, is overerased, its threshold voltage will be zero or negative, and background leakage current will flow through the transistor T.sub.2 as indicated at I.sub.2. The bitline current I.sub.BL is now no longer equal to I.sub.1, but is equal to the sum of I.sub.1 and the background leakage current I.sub.2.
In a typical flash EEPROM, the drains of a large number, for example 512, transistor cells such as illustrated in FIG. 1 are connected to each bitline (column). If a substantial number of cells on the bitline are drawing background leakage current, the total leakage current on the bitline can exceed the cell read current. This makes it impossible to read the state of a cell on the bitline and renders the memory inoperative.
FIG. 2 illustrates how the threshold voltages of the cells or bits in a flash EEPROM can differ substantially from each other following an erase operation as shown by a solid line curve which represents the numbers of cells having particular values of threshold voltage V.sub.T. It will be seen that the least erased cells will have a relatively high threshold voltage V.sub.T MAX, whereas the most overerased cells will have a low threshold voltage which is below a minimum acceptable value V.sub.T MIN that can be negative. The characteristic illustrated in FIG. 2 is known as the threshold voltage distribution.
FIG. 3 illustrates how the background leakage current of a cell varies as a function of threshold voltage. The lower (more negative) the threshold voltage, the higher the leakage current. It is therefore desirable to prevent cells from being overerased and reduce the threshold voltage distribution to as low a range as possible, with ideally all cells having the same high threshold voltage after erase on the order of 2 V.
It is known in the art to reduce the threshold voltage distribution by performing an overerase correction operation which reprograms the most overerased cells to a higher threshold voltage. This operation will result in the threshold voltage curve being altered to the shape indicated by broken line in FIG. 2 in which the threshold voltages of all of the cells are above the minimum acceptable value V.sub.T MIN. An overerase correction operation of this type is generally known as Automatic Programming Disturb (APD).
A preferred APD method which is referred to as Automatic Programming Disturb Erase (APDE) is disclosed in U.S. Pat. No. 5,642,311, entitled "OVERERASE CORRECTION FOR FLASH MEMORY WHICH LIMITS OVERERASE AND PREVENTS ERASE VERIFY ERRORS", issued Jun. 24, 1997 to Lee Cleveland. This patent is assigned to the same assignee as the present invention and is incorporated herein by reference in its entirety. The method includes sensing for overerased cells and applying programming pulses thereto which bring their threshold voltages back up to acceptable values.
Following application of an erase pulse, undererase correction is first performed on a cell-by cell basis by rows. The cell in the first row and column position is addressed and erase verified by applying 4 V to the control gate (wordline), 1 V to the drain (bitline), grounding the source, and using sense amplifiers to sense the bitline current and thereby determine if the threshold voltage of the cell is above a value of, for example, 2 V. If the cell is undererased (threshold voltage above 2 V), the bitline current will be low. In this case, an erase pulse is applied to all of the cells, and the first cell is erase verified again.
After application of each erase pulse and prior to a subsequent erase verify operation, overerase correction is performed on all of the cells of the memory. Overerase verify is performed on the bitlines of the array in sequence. This is accomplished by grounding the wordlines, applying typically 1 V to address the first bitline, and sensing the bitline current. If the current is above a predetermined value, this indicates that at least one of the cells connected to the bitline is overerased and is drawing leakage current. In this case, an overerase correction pulse is applied to the bitline. This is accomplished by applying approximately 5 V to the bitline for a predetermined length of time such as 100 .mu.s.
After application of the overerase correction pulse the bitline is verified again. If bitline current is still high indicating that an overerased cell still remains connected to the bitline, another overerase correction pulse is applied. This procedure is repeated for all of the bitlines in sequence.
The procedure is repeated as many times as necessary until the bitline current is reduced to the predetermined value which is lower than the read current. Then, the procedure is performed for the rest of the cells in the first row and following rows until all of the cells in the memory have been erase verified.
By performing the overerase correction procedure after each erase pulse, the extent to which cells are overerased is reduced, improving the endurance of cells. Further, because overerased cells are corrected after each erase pulse, bitline leakage current is reduced during erase verify, thus preventing undererased cells from existing upon completion of the erase verify procedure.
Although the APDE method is effective in eliminating overerased cells, it is limited in that since the sources and wordlines (control gates) of the cells are grounded during overerase correction, overerased cells will draw background leakage current while the overerase correction pulses are being applied. The leakage current requires the provision of a large power supply. In addition, background leakage current is also present during programming and creates similar problems.
These problems are exacerbated as the supply voltage V.sub.cc is reduced in step with the reduction of feature sizes of EEPROMs. The threshold voltages of the erased cells must be reduced to accommodate the lower values of V.sub.cc. This results in more cells in the low threshold voltage portion of the curve in FIG. 2 drawing leakage current.
In a sufficiently low V.sub.CC application, so many cells will draw leakage current that the total bitline leakage current during erase verify can exceed the value corresponding to an erased cell, even if the cell being verified is undererased. This makes it impossible to determine the state of a cell during erase verify and read, and renders the memory inoperative. This problem has remained unsolved in the prior art and has severely hindered the development of reduced voltage EEPROMs.
Another undesirable effect which becomes especially problematic at low values of V.sub.cc is that if V.sub.cc is applied directly to a wordline, it will be insufficient to enhance the channel of a selected cell such that a verify operation can be performed during erase. For this reason, a booster is provided to boost the wordline voltage to a value which is sufficiently higher than V.sub.cc that cell verification can be reliably performed. For a value of V.sub.cc =3 V, the wordline voltage is typically boosted to a value of approximately 4-5 V.
Voltages are applied to bitlines through pass transistors which enable individual bitline selection. The background leakage current loads down the charge pump and increases the voltage drop across the pass transistors, resulting in a lower drain voltage being applied to the cells. If the drain voltage becomes too low, which can result from excessive leakage current, the cell operation can become unstable and unreliable.